As one of the methods for testing semiconductor devices such as a very large scale integrated circuit (VLSI), a charged particle beam test system may be used to monitor voltages in internal nodes of the VLSI. A charged particle beam, such as an electron beam, is irradiated onto the surface of an integrated circuit under test (DUT) and the resultant secondary electron which represents the voltages and other states of the DUT is detected, thereby obtaining a voltage contrast image of the DUT on a display. A charged particle beam test system is advantageous for testing a high density and complex semiconductor chip because it can test such semiconductor chips without physically contacting thereto for probing input/output signals.
In a type of charged particle beam test systems, the secondary electron from DUT resulted by irradiation of the charged beam is sampled in a predetermined time sequence. An example of such a charged particle beam test system in the conventional technology is shown in FIGS. 5 and 6. In the example of FIG. 5, the charged particle beam test system includes a DUT driver 40, a burst sampling signal generator 50, a charged particle beam column 60, a signal processor 70, a test result memory 80, and a controller 90. The charged particle beam column 60 includes a charged particle beam generator such as an electron gun 62, a beam blanker 64, an X-Y beam deflector 65, a grid 66 and a secondary electron detector 68. At the bottom of the column 60, a semiconductor device under test (DUT) is placed on an X-Y stage 67. The burst sampling signal generator 50 includes a variable delay 52 and a burst pulse generator 54.
A charged particle beam such as an electron beam emitted from the electron gun 62 is irradiated on the surface of the DUT through the beam blanker 64 and the beam deflector 65. The beam blanker 64 controls blanking of the charged particle beam from the electron gun 62 thereby producing a pulsed charged particle beam. The beam deflector 65 deflects the charged particle beam from the electron gun 62 thereby allowing the beam to scan on the DUT. By moving the X-Y stage 67 in the X and Y directions, the irradiating position of the charged particle beam on the surface of the DUT can be controlled. The signal processor 70 provides a control signal which is provided to the grid 66 to control the amount of secondary electron emitted from the DUT. Such functions of the X-Y stage 67 and the grid 66 are not directly related to the point of the present invention.
The DUT driver 40 provides test signals 48 with predetermined timings to corresponding terminals of the DUT so that the circuit to be tested by the charged-particle beam be active. The DUT driver 40 also provides a trigger signal 51 to the burst sampling signal generator 50 to synchronize the test signals 48 to the DUT and the pulsed charged particle beam irradiated on the DUT. Typically, the DUT driver 40 is an IC tester which generates test patterns with various timings based on a software program.
Because the charged particle beam column 60 is relatively slow in its operational speed, a sampling method is used in testing the potential data of the DUT in high timing resolution. In this example, the burst sampling signal generator 50 provides N pulses to the beam blanker 64 for each trigger signal 51 from the DUT driver 40 to decrease the measuring time by 1/N. The burst sampling pulses have a time interval T which is large enough for the charge particle beam column 60 to respond.
Moreover, to acquire the test result data in high timing resolution, the start timing of such sampling pulses is made random or slightly shifted for each trigger signal. In this example, the burst sampling signal generator 50 is arranged to generate N burst pulses 58 every time when the trigger pulse 51 is received from the DUT driver 40. The start timing of the burst pulses, i.e., the time difference between the trigger signal and the first burst pulse is varied randomly or slightly for each set of burst pulses 58. The burst pulses 58 has a predetermined time period T and are produced by the burst pulse generator 54 at the randomly delayed or slightly shifted time after the trigger pulse 51 by the variable delay 52.
The operation of the burst sampling signal generator 50 is shown in FIG. 6A. The trigger pulse 51 to the sampling pulse generator 50 is generated in synchronism with the test signal 48 to the DUT. After the delay time Td specified by the variable delay 52, the first set of burst pulses 58 is generated by the burst pulse generator 54. The number of burst pulses is N and the burst pulses have the predetermined time interval T as shown in FIG. 6A.
In the example of FIG. 6A, each set of burst pulses starts by adding a delay time .DELTA.T to the delay time Td by the variable delay 52. Namely, the first set of burst pulses 58 is generated at the first delay time Td relative to the trigger pulse 51. The second set of burst pulses 58 is generated after a second delay time Td+.DELTA.T produced by the variable delay 52 relative to the second trigger pulse 51 pulse. The third set of burst pulses 58 is generated after a third delay time Td+2.DELTA.T produced by the variable delay 52 relative to the third trigger pulse 51. Similarly, the N-th set of burst pulses 58 is started after an N-th delay time Td+N.DELTA.T delayed from the N-th trigger pulse 51.
Each set of burst pulses 58 is applied to the beam blanker 64 of the charged particle beam column 60 so that the charged particle beam is irradiated in the form of the burst pulses. The burst sampling signal generator 50 also provides sampling pulse data 59a and address data 59b to the signal processor 70. The address data 59b shows address information relative to the timing of the trigger pulse 51 as shown in FIG. 6B. The signal processor 70 provides the address data to the test result memory 80 to store the test data therein representing the secondary electron responsive to the burst pulses. The sampling pulse data 59a may include the information on the type of data followed.
In the example of FIG. 6B, for the first pulse of the first set of burst pulses 58, the address data 59b for accessing the address "0" of the memory 80 is produced based on the trigger pulse 51 at the timing suitable to store the measured data corresponding to the first pulse. Further in this example, it is so arranged that after the time interval T, the address data 59b for accessing the address "8" is provided to the memory 80 through the signal processor 70 to store the measured data corresponding to the second pulse of the first burst pulses. In this manner, the address data for accessing every eight addresses is produced in the first set of burst pulses 58.
In the second set of burst pulses, the address data 59b is produced for accessing the address "1" at the time corresponding to an additional delay time .DELTA.T for storing the measured data corresponding to the first pulse of the second set of burst pulses. After the time interval T, the address data 59b for accessing the address "9" is provided to the memory 8 to store therein the measured data corresponding to the second pulse. In this manner, the address data for accessing every eight address is produced in the second set of burst pulses 58 at the timing shifted by the delay time .DELTA.T relative to the first set of burst pulses. The above noted process is repeated so that all of the memory addresses are filled with the measured data when the last set of burst pulses has been generated.
Since the burst pulses 58 are applied to the beam blanker 64 of the charged particle beam column 60 in the manner noted above, the charged particle beam is irradiated on the DUT in the form of the burst pulses. The portion of the DUT which is irradiated with the charged particle beam emits secondary electron representing the voltage in the irradiated portion. The secondary electron detector 68 detects the secondary electron from the DUT to obtain the waveforms as shown in FIG. 7A and integrates the detected signal in a manner shown in FIG. 7B. The secondary electron detector 68 converts the detected signal to digital data 69 which is provided to the signal processor 70 as shown in FIG. 5.
The waveforms of FIGS. 7A and 7B show the case where the charged particle beam from the electron gun 62 is not swept by the X-Y deflector 65 but fixedly irradiating the specified position on the DUT. Further, the waveforms of FIGS. 7A and 7B show the case where the voltage in the irradiated node of the DUT is a fixed DC voltage which is in a steady state rather than a transitional state. After testing the specified position of the DUT in the manner noted above, the charged particle beam is deflected by the X-Y deflector 65 to irradiate the next position on the DUT to measure the secondary electron emitted therefrom.
In receiving the detected data 69 from the secondary electron detector 68 as well as the sampling pulse data 59a and the address data 59b, the signal processor 70 processes and converts the detected data 69 to test result data 79. The signal processor 70 sends the test result data 79 and address data 78 which is basically the same as the address data 59b to the test result memory 80. Based on the data from the signal processor 70, the test result memory 80 stores the test result in the addresses specified in the manner shown in FIG. 6B.
In this manner, the test results are stored in the addresses of the memory 80 corresponding to the N burst pulses having the time interval T with one another. The time length between the trigger pulse 51 and the start of the burst pulses increases by the delay time .DELTA.T relative to the previous set of burst pulses as noted above with reference to FIGS. 6A and 6B. Namely, the delay time .DELTA.T corresponds to the timing difference between the two adjacent addresses of the memory 80. Thus, by repeating the predetermined sets of burst pulses, all of the test results will be stored in the corresponding addresses of the test result memory 80.
In this conventional technology, however, there arises a transient voltage error for at least first several burst pulses every time the set of burst pulses are applied to the DUT. Such a transient voltage error is illustrated in FIGS. 7A and 7B. In FIG. 7A, even when the DC voltage in the irradiated node of the DUT is a constant value, the amount of secondary electron detected by the secondary electron detector 68 varies with respect to the first several burst pulses. Thus, when the peak values of the detected voltage are integrated, the waveform of FIG. 7B showing the average voltage will be produced which is a curved or stepped line rather than a straight line.
This transient voltage error is considered to be caused by the temperature change of the charged particle beam test system or a time constant involving stray capacitors in the charged particle beam test system. Since the system is not operating during the period after the end of the previous burst pulses and before the start of the next burst pulse, such changes in the temperature may occur for the first several pulses in the set of burst pulses. Further, since the system has a period when it is not generating the charged particle beam and other period when the charged particle beam in the burst pulse form is generated, there exists a transient period caused by the stray capacitors in the system.
As a consequence, the conventional test method using the burst pulses involves the transient voltage error such as shown in FIGS. 7A and 7B. Therefore, the conventional charged particle beam test system is not appropriate for evaluating the potential contrast of the LSI which requires high measurement accuracy.